`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg [3:0]cnt;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt<=4'd0;
	end
	else begin
		if(valid_in)begin
			if(cnt<4'd15)
				cnt<=cnt+4'd1;
			else
				cnt<=4'd0;
		end
		else 
			cnt<=cnt;
	end
end

reg [119:0]data_out_r;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_out<='d0;
		data_out_r<='d0;
	end
	else if(valid_in)begin
		if(cnt==4'd5)begin
			data_out_r<={data_out_r[119:16],data_in[15:0]};
			data_out<={data_out_r,data_in[23:16]};
		end
		else if(cnt==4'd10)begin
			data_out_r<={data_out_r[119:8],data_in[7:0]};
			data_out<={data_out_r[111:0],data_in[23:8]};
		end
		else if(cnt==4'd15)begin
			data_out_r<={data_out_r[119:24],data_in[23:0]};
			data_out<={data_out_r[103:0],data_in[23:0]};
		end
		else begin
			data_out_r<={data_out_r[95:0],data_in[23:0]};
			data_out<=data_out;
		end
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out<=1'b0;
	end
	else if(valid_in)begin
		case(cnt)
			4'd5:valid_out<=1'b1;
			4'd10:valid_out<=1'b1;
			4'd15:valid_out<=1'b1;
			default:valid_out<=1'b0;
		endcase
	end
	else 
		valid_out<=1'b0;	
end

endmodule